It is known to provide a so-called mixed analog-digital LSI circuit which is constructed, for example, by incorporating an analog/digital converter (ADC) in a logic LSI. This type of LSI circuit, however, has had the problem that the noise generated during the operation of a logic circuit in the digital circuit block may adversely affect the accuracy of the ADC in the analog circuit block.
Incidentally, in recent years, LSI circuits having a plurality of circuit blocks that operate with different clock frequencies have been increasing in number, making it increasingly difficult to address the problem by the related art circuit configuration designed to operate with the same clock frequency.
More specifically, for example, in the case of a circuit in which a clock input dedicated to the digital circuit is provided separately from the sampling clock of the ADC so that the digital circuit that may become a noise source operates asynchronously with respect to the analog circuit, it has been difficult with the related art electric circuits to sufficiently reduce the adverse effects of the noise.
Patent Document 1: Japanese Laid-open Patent Publication No. H06-283999
Patent Document 2: Japanese Laid-open Utility Model Publication No. H05-011558